COMPUTER ORGANIZATION ARCHITECTURE CARL HAMACHER PDF

adminComment(0)
    Contents:

Computer organization and embedded systems / Carl Hamacher. His current research interests include computer architecture and field-. Carl Hamacher received his bestthing.info degree in engineering physics from the His research interests are in the areas of computer architecture, reliability of digital. Text Book Computer Organization by Carl Hamacher 5th Edition. Pages· · MB·2, Computer organisation and architecture(Carl Hamacher) .


Computer Organization Architecture Carl Hamacher Pdf

Author:NICKIE LEIDICH
Language:English, French, Arabic
Country:Nepal
Genre:Technology
Pages:576
Published (Last):25.02.2016
ISBN:255-2-51454-247-5
ePub File Size:17.44 MB
PDF File Size:11.85 MB
Distribution:Free* [*Sign up for free]
Downloads:24722
Uploaded by: LOREE

Computer Organization and Embedded Systems Carl Hamacher Zvonko interests include computer architecture and field-programmable VLSI technology. Home» Carl Hamacher» Computer Organisation» DOWNLOAD» edition» Fifth » FREE» PDF» Safwat Zaky» Zvonko Vranesic» Computer. Hamacher - Computer Organization (5th Ed) - Free ebook download as PDF File .pdf) or read book online Computer System Architecture by Morris Mano Third Edition 5e V. Carl Hamacher, Zvonko G. Vranesic, Safwat G. Zaky-Computer.

See section 2. Clear the high-order 4 bits of each byte to A program for the expression is: Memory word location J contains the number of tests, j, and memory word location N contains the number of students, n. The Base with index addressing mode R1,R2 is used to access the scores on a particular test. Register R1 points to the test score for student 1, and R2 is incremented by Stride in the inner loop to access scores on the same test by successive students in the list.

Move J,R10 Initialize outer loop counter R10 to j. Clear R2 Clear index register R2 to zero. Clear R0 Clear sum register R0 to zero. Add 4,R1 Increment base register to next test score for student 1. The dot product program in Figure 2. Suppose that R1 and R2 are retained as pointers to the A and B vectors. Linked list version of the student test scores program: Assume that the subroutine can change the contents of any register used to pass parameters.

Multiply 4,R4 Use R4 to contain distance in bytes Stride between successive elements in a column. Return Return to calling program. The Move instruction places into memory word location when the instruction is executed as part of a program.

That is, the next item must be entered at the beginning of the memory region, assuming that location is empty. The IN pointer points to the location where the next byte will be appended to the queue. If the queue is not full with k bytes, this location is empty, as shown in the diagram.

The OUT pointer points to the location containing the next byte to be removed from the queue.

If the queue is not empty, this location contains a valid byte, as shown in the diagram. But the IN pointer must also be pointing to location 1, because following the wraparound rule it must point to the location where the next byte will be appended.

Thus, in both cases, both pointers point to location 1; but in one case the queue is empty, and in the other case it is full. Restore contents of IN to contents of LOC and indicate failed append operation, that is, indicate that the queue was full.

Otherwise, store new item at LOC. Remove operation: Indicate failed remove operation, that is, indicate that the queue was empty. Use the following register assignment: Compare R1,R2 Check if queue is empty.

Recursion is not supported. The Return instruction pops this value into the program counter. This supports recursion, that is, when the subroutine calls itself. Assume that register SP is used as the stack pointer and that the stack grows toward lower addresses.

Also assume that the memory is byte- addressable and that all stack entries are 4-byte words. Initially, the stack is empty. If the ID of the new record matches the ID of the Head record of the current list, the new record will be inserted as the new Head. If the ID of the new record matches the ID of a later record in the current list, the new record will be inserted immediately after that record, including the case where the matching record is the Tail record.

In this latter case, the new record becomes the new Tail record. Modify Figure 2. If the list is not empty, the following happens. Replace Figure 2. ARM 3. The stack pointer R1 is returned to its original value of These two numbers are then added and the sum is placed in register R4.

Note that it cannot be generated by the rotation of any 8-bit value. The following two instructions perform the desired operation: Use register R0 as a counter register and R1 as a work register. Program trace: Assume bytes are unsigned 8-bit values. The inner loop checks for a match at each possible position. R0 and exit. To change to uppercase, we need to change bit b5 from 1 to 0.

Computer Organization by Carl Hamacher 5th [Studypoint4u.com]

The Post-indexed addressing mode [R2],R3,LSL 2 is used to access the successive scores on a particular test in the inner loop. Therefore, register R2 is incremented by the Stride parameter on each pass through the inner loop. Assume that the subroutine can change the contents of any registers used to pass parameters.

STR R5,[R13, 4]! Save [R5] on stack. This program is similar to Figure 3. Assume that most of the time between successive characters being struck is spent in the three-instruction wait loop that starts at location READ. The stack frame structure shown in Figure 3. It echoes the characters back to a display as well as reading them into memory. The stack frame format used is like Figure 3.

A possible main program is: MOV R5, 3 Same code as. See the solution to Problem 2. Register assignment: The record pointer is register R0, and registers R1, R2, and R3, are used to accumulate the three sums, as in Figure 2. Assume that the list is not empty. If the ID matches that of a later record, it will be inserted immediately after that record, including the case where the matching record is the Tail.

Modify Figure 3. If the list is empty, the result is unpredictable because the second instruc- tion compares the new ID with the contents of memory location zero. Replace Figure 3. One memory access is needed to fetch the instruction and 4 to execute it.

Computer Organization 5th Edition, Carl Hamacher, Zvonko

L 9,D2 The number of bits shifted must be less than 8. B The destination operand must be a data register.

Also the source operand is outside the range of signed values that can be represented in 8 bits. W 83 5 5 0 after 2nd ADD. W 4 5 0 after 3rd ADD. W 3 5 0 after 4th ADD. W 34 2 5 0 after 5th ADD. W 1 5 0 after last MOVE. We have assumed that the assembler uses short absolute addresses. L, etc. Otherwise, 3 more words would be needed. Program 2 destroys the original list. A program for string matching: Therefore, the largest value of n that this program can handle is 14, because the largest number that can be stored in a byte is Assume that most of the time between successive characters being struck is spent in the two-instruction wait loop that starts at location READ.

Assume that register A4 is used as a memory pointer by the main program. B CR,D0 Check for end-of-line character. W 3, A0 Wait for character. B A1 ,D0 Load character into D0. RTS Return. W 3, A2 Wait for display. B D0, A3 Send character to display. A stack structure like that shown in Figure 3. The main program uses register A0 as a memory pointer, and uses register D0 to hold the character read. L 16 A7 ,D0 Load long word containing character into D0. B D0, A1 Send character to display.

L 1,A1 Increment A1 Modulo k. L A1,A2 Check if queue is full. B D0,[A5] Append byte. L A1,A2 Check if queue is empty. Using the same assumptions as in Problem 3. A program to reverse the order of bits in register D2: The trace table is: Assume the list address is passed to the subroutine in register A1. When the subroutine is entered, the number of list entries needs to be loaded into D1.

Because addresses must be incremented or decremented by 2 to handle word quantities, the address mode A1,D1 is no longer useful. Also, since the initial address points to the beginning of the list, we will scan the list forwards.

Use D4 to keep track of the position of the largest element in the inner loop and D5 to record its value. We will use registers D1, D2, and D3 to accumulate the three sums. Assume also that the list is not empty. Hence, the BNE instruction will test the correct values. In the program of Figure 3. Modify the program as follows.

If the ID of the new record is less than that of the head, the program in Figure 3. If the list is not empty, the program continues until A2 points to the Tail record. To correct behavior, modify the program as follows. Intel IA 3. Initial memory contents are: Only one operand can be in memory. Scale factor can only be 1, 2, 4, or 8. An immediate operand can not be a destination. ESP cannot be used as an index register. To change characters from lowercase to uppercase, change bit b5 from 1 to 0.

Append routine: Remove routine: Assume that register ECX is used as a memory pointer by the main pro- gram. RET Return. The potential advantage is that the inner loop should execute faster.

Otherwise, the same input data would be read a second time. A subroutine is called by a program instruction to perform a function needed by the calling program. An interrupt-service routine is initiated by an event such as an input operation or a hardware error.

Hence, it must not affect any of the data or status information relating to that program. If execution of the interrupted instruction is to be completed after return from interrupt, a large amount of information needs to be saved. This includes the contents of any temporary registers, intermediate results, etc. An alternative is to abort the interrupted instruction and start its execution from the beginning after return from interrupt.

In this case, the results of an instruction must not be stored in registers or memory locations until it is guaranteed that execution of the instruction will be completed without interruption. When an interrupt request is received from either A or B, interrupts from the other device will be automatically disabled until the request has been serviced. Input-output organization is developed in Chapter 4. Interrupts and direct-memory access methods are described in detail, including a discussion of the role of software interrupts in operating systems.

Caches and multiple-module memory systems are explained as ways for increasing main memory bandwidth. Caches are discussed in some detail, including perfonnance modeling.

Vutual-memory systems, memory management, and rapid address translation techniques are also presented. Magnetic and optical disks are discussed as components in the memory hierarchy.

Chapter 6 treats the arithmetic unit of a computer. Logic design for fixed-point add, subtract, multiply, and divide hardware, operating on 2's-complement numbers, is described.

Lookahead adders and high-speed multipliers are explained, including descriptions of the Booth multiplier recoding and carry-save addition techniques. Floatingpoint number representation and operations, in the context of the IEEE Standard, are presented. Chapter 7 begins with a register-transfer-level treatment of the implementation of instruction fetching and execution in a processor. This is followed by a discussion of processor implementation by both hardwired and microprogrammed control.

PREFACE Chapter 8 provides a detailed coverage of the use of pipelining and multiple function units in the design ofhigh-perfonnance processors. The role of the compiler and the relationship between pipelined execution and instruction set design are explored. Today there are many more processors in use in embedded systems than in generalpurpose computers. System ifttegration issues, interconnections, and real-time software are discussed.

Chapter 10 presents peripheral devices and computer interconnections.

Copyright 2002 by The McGraw-Hill Companies, Inc. All rights reserved.

Commonly used communication links, such as DSL, are discussed. This chapter highlights the design changes that led to higher perfonnance. Chapter 12 extends the discussion of computer organization to large systems that use many processors operating in parallel.

Interconnection networks for multiprocessors are described, and an introduction to cache coherence controls is presented. Sharedmemory and message-passing schemes are discussed. They include the following: Chapter 2 of the fourth edition has been split into two chapters - Chapters 2 and 3 - in the fifth edition. More programming examples for typical tasks, both numeric and non-numeric, are provided. The discussion of the role of pipelining and multiple functional units in processor design has been extended significantly.

A new chapter on embedded-processor systems has been added.A program to reverse the order of bits in register D2: To allow interrupt nesting, the mask must be set to 3 at the beginning of ISR.

Notify me of new posts by email. STR R5,[R13, 4]! W 34 2 5 0 after 5th ADD. The circuit requires careful initialization, because one and only one output of register A must be equal to 1. Caches are discussed in some detail, including perfonnance modeling. Append routine:

EMANUEL from Honolulu
Review my other posts. I have only one hobby: tag rugby. I do enjoy studying docunments ferociously .
>