VESA DisplayPort Standard. Version 1, Revision 2. January 5, Purpose. The purpose of this document is to define a flexible system and apparatus. Page 2 of Table of Reuced Bit Rate Cable-Connector Assembly Specification DisplayPort Version 1, Revision 1a January 11, 2nd The RJ PDF is a Gaussian. With the publication of DisplayPort Standard Specification Ver . DP v ( Gbps). DP va. ( Gbps). HDMI MHz Clock.
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DisplayPort (DP) is a digital display interface developed by a consortium of PC and chip . The DisplayPort a standard can be downloaded for free from the VESA website. devices and portable media players, which includes 2-lane DisplayPort va connection. . Archived from the original (PDF) on 8 April . 07, The Video Electronics Standards Association (VESA) today formally DisplayPort v is backward compatible with existing DisplayPort va systems . VESA DisplayPort StandardVersion 1, Revision 2January 5,
The values written in the register are applied at the video frame boundary only. Enable the transmission of secondary link information. Reads from this register always return 0x0. Returns the unique identification code of the core and the current revision level. Initiates AUX channel commands of the specified length. When this bit is set to 1, the source will initiate Address only transfers STOP will be sent after the command.
The range of the register is 0 to 15 indicating between 1 and 16 bytes of data.
Specifies the address for the current AUX channel command. Indicates an overflow in the user FIFO. The event may occur if the video rate does not match the TU size programming.
This bit clears upon read. Contains the raw signal values for those conditions which may cause an interrupt. Reply data is read from the FIFO starting with byte 0.
The number of bytes in the FIFO corresponds to the number of bytes requested.
Reply code received from the most recent AUX Channel request. Note: The core will not retry any commands that were Deferred or Not Acknowledged. Writing to this register clears the count. Source core interrupt status register. A read from this register clears all values. The duration of the pulse can be determined by reading 0x When set to a 1, the specified interrupt source is masked. This register resets to all 1s at power up.
Returns the total number of data bytes actually received during a transaction. This register does not use the length byte of the transaction header. The bit is set to '0' when the AUX transaction request controller is idle. The bit is '0' otherwise. The AUX reply controller sets this bit to '1' when a complete and valid reply transaction has been received.
Specifies the total number of clocks in the horizontal framing period for the main stream video signal. Provides the total number of lines in the main stream video frame. Provides the polarity values for the video sync signals.
Sets the width of the horizontal sync pulse. Sets the width of the vertical sync pulse. Horizontal resolution of the main stream video source. Vertical resolution of the main stream video source. Number of clocks between the leading edge of the horizontal sync and the start of active data. Number of lines between the leading edge of the vertical sync and the first line of active data.
Miscellaneous stream attributes. M value for the video stream as computed by the source core. If synchronous clocking mode is used, this register must be written with the M value. Sets the size of a transfer unit in the framing logic On reset, transfer size is set to Note that bit 0 cannot be written the transfer unit size is always even. N value for the video stream as computed by the source core. If synchronous clocking mode is used, this register must be written with the N value. Selects the width of the user data input port.
This register is used to translate the number of pixels per line to the native internal bit datapath. Informs the DisplayPort transmitter main link that the source video is interlaced.
This bit must be set to a '1' for the proper transmission of interlaced sources. The calculation should be done based on the DisplayPort specification. This register is used to hold the fractional component.
This allows enough data to be buffered in the input FIFO. Reset the transmitter PHY. Clear to release. Set the pre-emphasis level for lane 0 of the DisplayPort link. Up to eight levels are supported for a wide variety of possible PHY implementations. The mapping of the four levels supported by the DisplayPort standard to the eight levels indicated here is implementation specific. Controls the differential voltage swing for lane 0 of the DisplayPort link.
The mapping of the four levels supported by the DisplayPort specification to the eight levels indicated here is implementation specific. Enable the pseudo random bit sequence 7 pattern transmission for link quality assessment. Control PHY Power down. One bit per lane. When set to 1, moves the GT to power down mode. Set the pre-cursor level for lane 0 of the DisplayPort link non-spartan-6 devices.
The mapping of the four levels supported by the DisplayPort standard to the 32 levels indicated here is implementation specific. Set the post-cursor level for lane 0 of the DisplayPort link non-spartan-6 devices. Provides the current status from the PHY. The DisplayPort Audio registers are listed in Table Enables audio stream packets in main link and provides buffer control.
Used to input active channel count. Transmitter collects audio samples based on this information. No protection is provided for wrong operations by software. M value of audio stream as computed by transmitter.
N value of audio stream as computed by transmitter. Extended packet is fixed to 32 Bytes length.
The controller has buffer space for only one extended packet. This is a key-hole memory. So, nine writes to this address space is required. In the case of multiple bit fields, a lock bit may be maintained to prevent the status values from being updated while the read is occurring. Any bits not specified in Table are to be considered reserved and will return '0' upon read. Enable the receiver 1 - Enables the receiver core.
Asserts the HPD signal when set. Enables the display timing generator in the user interface. The DTG should be disabled when the core detects the no-video pattern on the link. Configures the number of pixels output through the user data interface. The Sink controller programs the pixel width to the active lane count default. User can override this by writing a new value to this register. Valid for designs with 2 or 4 lanes. Valid for designs with 4 lanes only. When set to a '1', the specified interrupt source is masked.
Video interrupt is set after a delay of eight video frames following a valid scrambler reset character. Allows the host to instruct the receiver to pass the MSA values through unfiltered. When set to '1', two matching values must be detected for each field of the MSA values before the associated register is updated internally.
Provides a running total of errors detected on inbound AUX Channel requests. Provides a running total of the number of AUX requests received. Instructs the receiver core to assert an interrupt to the transmitter using the HPD signal. A read from this register always returns 0x Set to '1' to send the interrupt through the HPD signal. The HPD signal is brought low for us to indicate to the source that an interrupt has been requested. Width of the recovered AUX clock from the most recent request.
Provides the most recent AUX command received. Contains the address field of the most recent AUX request. The length of the most recent AUX request is written to this register. The length of the AUX request is the value of this register plus one.
Transaction lengths from 1 to 16 bytes are supported. For address only transactions, the value of this register will be 0.
Indicates the cause of a pending host interrupt. The horizontal and vertical resolution parameters are monitored for changes. The display timing generator control logic outputs a fixed length, active-high pulse for the horizontal sync.
The timing of this pulse may be controlled by setting this register appropriately. The default value of this register is 0x0f0f.
Fast I2C mode clock divider value. Valid only for DPCD 1. Indicates the presence of EDID information for the video stream. Indicates the presence of EDID information for the audio stream. General byte for passing remote information to the transmitter. A write of 0x0 to this register has no effect.
Refer to DPCD register section of the specification for more details. Reads from this register reflect the state of DPCD register. DPCD register bit to inform the transmitter that video data is not supported. DPCD register bit to inform the transmitter that audio data is not supported 0 - Set to '1' when audio data is not supported.
Reserved for v1. Allows the user to setup GUID if required from host interface.
Valid for DPCD1. This status bit indicates an overflow of the user data FIFO of pixel data. This event may occur if the input pixel clock is not fast enough to support the current DisplayPort link width and link speed. Provides a mechanism for the host processor to monitor the state of the video data path. This bit is set when vsync is asserted.
At power up, this register has a value of 0x3. This value must be set to a value of 0 before the receiver core will function properly. Provides status for the receiver core PHY. This register controls the reset of the PHY when electrical idle is detected.
VESA ratifies DisplayPort 1.4 standard
The electrical idle condition happens when the link is not connected. This logic is enabled for Spartan-6 devices only. These bits allow the receiver core to conditionally power down specific lanes of the PHY if supported for a particular technology implementation. These bits should be written only after the training process has been completed and the link is stable.
Some DisplayPort implementations require the transmitter to set a minimum voltage swing during training before the link can be reliably established. The internal training logic will force training to fail until this value is met. This register enables audio stream packets in main link. Total of eight words should be read. Info frame data is copied into these registers read only.
M value of audio stream as decoded from Audio time stamp packet by the sink read only.
N value of audio stream as decoded from Audio time stamp packet by the sink read only. Resets automatically after all words 9 are read. Blocks new packet until host reads the data. Used for debugging purpose.
Resets automatically after all info words eight are read. Packet length is fixed to 32 bytes in Sink controller. User should convey this information to Source using the vendor fields and ensure proper packet size transmission is done by the Source controller. Total of nine words should be read. So, nine reads from this address space is required. Link bandwidth setting. The chip on the board converts the voltage levels generated by the dual-mode DisplayPort device to be compatible with a DVI monitor.
Multiple displays on single DisplayPort connector DisplayPort 1. This function requires either monitors that are capable of DisplayPort 1. The first MST hub became available in September , enabling up to 3 displays to be connected to a single DisplayPort connector. It is important to note that these are only claims.
Functions and Features
Whether these claims are relevant will likely be decided in a US court. Please help to clean it up to meet Wikipedia's quality standards. Where appropriate, incorporate items into the main body of the article. DisplayPort 1.
46" MultiSync X464UNS / X464UN / X464UNV
It also has the ability to share this bandwidth with multiple streams of audio and video to separate devices. However, they predicted that the figure for commercial desktops would grow to Shortly after announcing Mini DisplayPort, Apple announced that it would license the connector technology with no fee. This new standard will be physically smaller than the currently available mini DisplayPort connectors. The standard was expected to be released by Q2 Indicates the cause of a pending host interrupt.
Total number of active video lines in a frame of video. Tells the receiver core how many video clock cycles will occur between leading edges of the horizontal sync pulse. Reply code received from the most recent AUX Channel request.
See Selecting the Pixel Interface in Chapter 3 for more information on how to select the appropriate pixel interface.
Number of clocks between the leading edge of the horizontal sync and the start of active data.
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